The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor." One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
While the invention is described in terms of DRAMs, this is merely the preferred embodiment for which the inventive techniques were developed. DRAM process techniques are also applicable to related semiconductor circuit devices, including video random access memories (VRAMs) and other multiport RAMS, and other devices which use DRAM design techniques, such as optical sensing arrays. Significantly, DRAM process techniques are usually applicable to other types of semiconductor devices as well. In this respect, DRAM technology is considered to be a "driving technology" for other integrated circuit technology, and therefore the inventive techniques are expected to be applicable for other types of integrated circuits.
Producing DRAM IC memory circuits is a high volume business, in which process efficiency and manufacturability as well as product quality, reliability, and performance are essential key factors. This invention dramatically advances the "state of the art" in a number of ways in these areas.
The reverse poly DRAM process dramatically reduces the number of process steps, including masking steps, which has a direct impact on the cost, reliability, and manufacturability of the product. Latest generation DRAM products require scaling down to finer and finer geometries. This has a big impact on the cost of doing a photolithographic step. The source of this added cost comes from many sources. There are high capital costs associated with "state of the art" photolithographic equipment. Finer geometries require more complex photo processing in terms of more photo process steps per level and more equipment required, adding cost and using expensive ultra clean room floor space. Defect density is inevitably increased with each additional photomasking layer and compromises line yield, probe yield, and reliability. All photo layers require a subsequent step, either implant or etch. These are added steps adding to cost.
In a reverse poly DRAM process, it is possible to avoid extra mask steps for V.sub.T adjust. In DRAM applications the threshold voltage of the array access transistors may have separate requirements from the peripheral transistors. The access devices generally need a higher threshold than the periphery to optimize dynamic refresh characteristics. Peripheral transistors are optimized at reduced threshold values for maximum high speed performance. The conventional solution to this is to separately adjust the threshold of these two groups of transistors using a photomasking level. The reverse poly DRAM process has been designed in terms of thermal cycles and layout such that these two criteria are simultaneously met without a separate tailoring threshold adjust implant masking step.
It is desired to improve yield and reliability and reduce manufacturing costs. This can be accomplished by reduced cycle times through fabrication, reduced total process inventory needed for a given run rate, more rapid response to process changes in volume quantities, more repeatable performance, and less number of steps to introduce variation. The process is shrinkable for subsequent generation products and the process flow fits in well with subsequent CMOS high density DRAM processes. The transistor structure is fully shrinkable while maintaining strong "long channel" characteristics, high performance, and minimal degradation with time (high reliability).
The process is compatible with today's IC fabrication equipment, not requiring exotic new equipment. It avoids problems with poly "stringers" or "sticks," a common problem with conventional DRAM process technology. The process reduces the number of high current implants from a conventional 2 to only 1 implant. This is a costly step in terms of both throughput and machine cost and is greatly advantageous to minimize. Self alignment of the cell capacitor dielectric region makes possible the use of a cell capacitor dielectric with reduced oxide thickness from the transistor gate oxide without having to define this with another masking level.
This same concept also makes it possible to use an alternative cell capacitor dielectric material with higher dielectric permeativity than conventional silicon dioxide. A higher permeativity dielectric results in increased cell capacitance per unit area. Higher cell capacitance improves immunity to single event upsets due to alpha particles or cosmic radiation. This results in higher operational reliability. It also reduces the amount of surface area needed for the cell capacitor, thus allowing for greater shrink and smaller die size. No extra photomasking step is required for this feature.
Poly 1 is used for the transistor poly and Poly 2 is used for the cell field plate poly. This is opposite of most other DRAM processes. As mentioned above, this approach offers advantages. The transistor poly photo patterning and etch critical dimension control is improved due to lack of concern for "stringers" and extra topography. "Stringer" problems are minimized since they are a factor only during Poly 2 etch.
Poly 2 etch for the reverse poly DRAM process is for patterning of the cell field plate which is a noncritical etch and can be done by a number of isotropic means. This insures complete etch removal of "stringers." The extra topography seen at Poly 2 etch is less a factor due to the less stringent cell plate poly etch tolerances required. Self-alignment is possible between the cell capacitor region and the access gate active channel region. There is less susceptibility to field oxide thinning between Poly 1 and Poly 2. The high current/high dose arsenic S/D implant is done prior to cell capacitor formation. This spares the cell cap of having to withstand the electric field stress present due to charging effects associated with the S/D implant. This is a major factor as cell dielectrics continue to thin and become more and more sensitive to E-fields present during processing. The reverse poly DRAM process also offers the following product performance advantages. The invention makes possible use of advanced transistor structures using LDD with flexibility for re-optimization when shrinking in the future. The transistor structure also minimizes high drain electric fields thus helping preserve device stability and long term reliability. The reverse poly DRAM process is highly compatible with subsequent generation (multi-megabit) CMOS DRAMs allowing multi-generation parts to run in the same Fabrication area. Flexibility in cell capacitor dielectric is made possible by having the option of independently varying the transistor gate oxide independent of the cell capacitor dielectric. This flexibility is made possible without adding a photomasking step.
A reverse poly process was developed, initially for an NMOS process in order to reduce mask steps and provide improved alignment of circuit components formed by the multiple mask steps of a DRAM process. An embodiment of that process which used two polysilicon layers is described in U.S. Pat. No. 4,871,688.
In that embodiment, a first layer of poly which was deposited is used for the transistor poly and a second layer of poly which was deposited is used for the cell field plate poly. This is opposite of most other DRAM processes, and has several advantages:
1) The transistor poly etch is always a critical etch step as its critical dimension has a strong influence on device parameters. It is done early in the reverse poly DRAM process where there is minimal topography. This provides the advantages of best control and repeatability of fine line patterning.
2) It avoids problems associated with residual poly after poly etch known as "stringers" or "sticks." These are caused by re-entrant areas remaining after a conventional Poly 1 oxidation. Anisotropic etch of Poly 2 can leave residual poly in these areas, resulting in Poly 2-to-Poly 2 shorts. This places extra constraint on the transistor Poly 2 etch of a conventional flow where critical dimension control, stringer elimination, and extra topography must all be dealt with simultaneously. The reverse poly DRAM process avoids this problem by having transistor poly on the first poly.
3) The second poly on the reverse poly DRAM process is for the cell plate and does not have the critical dimensional tight tolerance requirements that the transistor poly has. Thus it is possible to use isotropic processes for etch of the cell plate poly easily eliminating "stringer" problems. The extra topography present at Poly 2 is more easily tolerated with the less stringent cell plate poly etch tolerance requirements.
4) The Poly 1 access device is tungsten silicided on top of Poly 1 and the spacer oxide on the sidewall.
5) In any general process flow, isolation field oxide thinning is encountered in processing between the Poly 1 and Poly 2 levels. This results in reduced parasitic field device threshold and thus compromises the integrity of the electrical isolation. This can be a problem for the conventional (prior art) process flow where the transistor poly (Poly 2) sees the thinnest field oxide. With common bootstrapping and double bootstrapping circuit techniques used on DRAMs, voltages of 12-15 volts at V.sub.CC =6 V are possible on some transistor poly gate circuit nodes. This can compromise high V.sub.CC margin. For the present invention, the transistor gate poly is formed from Poly 1. Minimal field oxide thinning is seen prior to Poly 1 deposition thus insuring an adequate field oxide thickness for transistor poly nodes. The normal thinning of field oxide seen prior to Poly 2 is not detrimental on the reverse poly DRAM process since Poly 2 is used only for the cell plate for the capacitor which is biased at DC ground.
6) The high current/high dose Arsenic S/D implant is done prior to cell capacitor formation. This spares the cell cap of having to withstand the electric field stress present due to charging effects associated with the S/D implant. This is a major factor as cell dielectrics continue to thin and become more and more sensitive to E-fields present during processing.
7) Transistor formation on the reverse poly DRAM process utilizes a unique technique for lightly doped drain (LDD) formation. The LDD regions are defined using an oxide spacer. This approach makes possible a dramatic reduction in device length without incurring the detrimental "short channel" effects seen with conventional approaches. Also, high electric field hot electron and hot hole effects are greatly reduced. This makes for more stable device characteristics over time and thus greatly improves device reliability. Thickness of the spacer is easily changed allowing greater flexibility for device re-optimization when shrinking.
8) Cell capacitance can be increased without adding masking steps using this reverse poly DRAM process sequence. The cell capacitor dielectric is formed after the transistors have been formed and encapsulated in oxide, top and side. Poly 2 is then deposited and etched. After the Poly 2 etch the dielectric is etched away from regions where the Poly 2 had been etched away. This self-aligns the cell dielectric underneath to the cell poly field plate.
9) The reverse poly DRAM process results in the manufacture of memory circuits in less photomasking steps than had previously been required. Additionally, fewer levels require stringent alignment and critical dimension control. The remaining levels are noncritical and afford rapid throughput with less stringent specifications. No extra mask step for V.sub.T adjust is required. This process requires only one high current implant, saving machine cost and floor space.
10) The reverse poly DRAM process flow is highly compatible with CMOS high density DRAM processes. This allows for ease in mutually running NMOS and CMOS steps together in the same fabrication area. Many of the furnace recipes, etch recipes, photo recipes, implants, and sputter recipes are identical, allowing NMOS and CMOS to run side by side. This last feature is particularly significant in the present invention, because the present invention is directed to a CMOS process.
In many transistor circuits, it is necessary to form both n channel transistors and p channel transistors, in a complimentary metal oxide semiconductor (CMOS) circuit. The present invention is directed to using the reverse poly process in fabrication of CMOS circuits.